Additive Multiply Module Architecture for Low Power 8-Bit Multipliers in VLSI

Vasudeva G, Gopal Chandra Sarkar, Aniket Magadum, Mohammed Asif, Adarsh Khot, B H M Siddesh

2025

Abstract

Multipliers are fundamental in digital signal processing and VLSI systems, directly affecting power, area, and speed. This paper presents the design and FPGA implementation of an 8-bit multiplier using Additive Multiply Module (AMM) architecture aimed at low-power, high-efficiency applications. The proposed AMM-based design is developed and verified on an FPGA and its experimental performance is benchmarked against conventional Wallace Tree and Dadda multipliers. Results confirm that the AMM multiplier not only reduces power consumption—but also achieves competitive area and delay—making it well-suited for modern embedded and IoT VLSI design environments.

Paper Citation

in Harvard Style

G V., Sarkar G., Magadum A., Asif M., Khot A. and Siddesh B. (2025). Additive Multiply Module Architecture for Low Power 8-Bit Multipliers in VLSI. In Proceedings of the 2nd International Conference on Advances in Electrical, Electronics, Energy, and Computer Sciences - Volume 1: ICEEECS; ISBN 978-989-758-783-2, SciTePress, pages 192-197. DOI: 10.5220/0014379900004848

in Bibtex Style

@conference{iceeecs25,
author={Vasudeva G and Gopal Chandra Sarkar and Aniket Magadum and Mohammed Asif and Adarsh Khot and B H M Siddesh},
title={Additive Multiply Module Architecture for Low Power 8-Bit Multipliers in VLSI},
booktitle={Proceedings of the 2nd International Conference on Advances in Electrical, Electronics, Energy, and Computer Sciences - Volume 1: ICEEECS},
year={2025},
pages={192-197},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0014379900004848},
isbn={978-989-758-783-2},
}

in EndNote Style

TY - CONF

JO - Proceedings of the 2nd International Conference on Advances in Electrical, Electronics, Energy, and Computer Sciences - Volume 1: ICEEECS
TI - Additive Multiply Module Architecture for Low Power 8-Bit Multipliers in VLSI
SN - 978-989-758-783-2
AU - G V.
AU - Sarkar G.
AU - Magadum A.
AU - Asif M.
AU - Khot A.
AU - Siddesh B.
PY - 2025
SP - 192
EP - 197
DO - 10.5220/0014379900004848
PB - SciTePress