Innovative 4-Bit Nano Processor Design Leveraging 16nm Transmission Gates

R Ravindraiah, A Chaithanya Lakshmi, P Padmini, G Sravanthi

2025

Abstract

The rapid evolution of VLSI technology has led to significant improvements in transistor scaling and performance. However, efficient current flow management between source and drain terminals remains a challenge. To address this, Transmission Gates (TG) have been integrated into 16nm technology, offering improved current control, power efficiency, and area optimization. This paper presents the design and analysis of a 4-bit Nano processor using Tanner EDA tools, focusing on power, area, and delay enhancements. The processor includes a 4-bit Arithmetic Logic Unit (ALU) composed of basic and universal gates, a high-speed Carry Skip Adder (CSA), a Vedic Multiplier, and a Multiplexer (MUX), all optimized to minimize power consumption and area overhead. For validation, Design Rule Check (DRC) and Layout Vs Schematic (LVS) verification are conducted before fabrication. The ALU is simulated using 16nm TG-based technology and compared with conventional 16nm CMOS technology. Results demonstrate that the TG-based design reduces MOSFET count from 800 to 680 (15% reduction), decreases delay from 0.519ns to 0.48008ns (~7.6% improvement), and lowers maximum power consumption from 0.1975656 µW to 0.1885975 µW (~4.5% improvement), while maintaining an average power consumption of ~1.79 µW.

Paper Citation

in Harvard Style

Ravindraiah R., Lakshmi A., Padmini P. and Sravanthi G. (2025). Innovative 4-Bit Nano Processor Design Leveraging 16nm Transmission Gates. In Proceedings of the 1st International Conference on Research and Development in Information, Communication, and Computing Technologies - ICRDICCT`25; ISBN 978-989-758-777-1, SciTePress, pages 660-665. DOI: 10.5220/0013918400004919

in Bibtex Style

@conference{icrdicct`2525,
author={R Ravindraiah and A Chaithanya Lakshmi and P Padmini and G Sravanthi},
title={Innovative 4-Bit Nano Processor Design Leveraging 16nm Transmission Gates},
booktitle={Proceedings of the 1st International Conference on Research and Development in Information, Communication, and Computing Technologies - ICRDICCT`25},
year={2025},
pages={660-665},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0013918400004919},
isbn={978-989-758-777-1},
}

in EndNote Style

TY - CONF

JO - Proceedings of the 1st International Conference on Research and Development in Information, Communication, and Computing Technologies - ICRDICCT`25
TI - Innovative 4-Bit Nano Processor Design Leveraging 16nm Transmission Gates
SN - 978-989-758-777-1
AU - Ravindraiah R.
AU - Lakshmi A.
AU - Padmini P.
AU - Sravanthi G.
PY - 2025
SP - 660
EP - 665
DO - 10.5220/0013918400004919
PB - SciTePress