Advancing Digital Design: Reversible Pipelined ALU Synthesis for Efficient RTL Logic

R. Ravindraiah, Bhupalam Sai Deeraj, Ammaladinne Bharathsimha Reddy, Manchineella Manikanta

2025

Abstract

Since reversible logic is a method to reducing energy dissipation in digital circuits, it has opened up possibilities in low-power computing, quantum computing and nanotechnology. In this work we investigate the synthesis of reversible pipelined Arithmetic Logic Units for efficient Register Transfer Level logic. But conventional ALUs dissipate energy and lose information because they use irreversible logic. Traditional logic gates like op-amps and RC circuits are both low-scalability, high-latency, and consume enormous amounts of power. Pipelining at Reversible Logic level has emerged as an attempt to improve computing performance and minimize power consumption. The methodology leverages reversible gates (Fredkin, Toffoli, and Peres) for arithmetic and logical operations, in addition to elevations, architectures, and synthesis methods for minimizing quantum cost, garbage outputs, and latency. Compared to traditional ALUs, the Xilinx Vivado_implemented design has lower power consumption, lower latency and higher performance. The proposed study shows the potential of reversible logic application in quantum computing and next-generation low-power digital computers. Statistical analysis of empirical results indicates that the proposed method reversible ALU reduces power consumption by 35% and latency by 25% when compared to traditional irreversible ALU designs.

Paper Citation

in Harvard Style

Ravindraiah R., Deeraj B., Reddy A. and Manikanta M. (2025). Advancing Digital Design: Reversible Pipelined ALU Synthesis for Efficient RTL Logic. In Proceedings of the 1st International Conference on Research and Development in Information, Communication, and Computing Technologies - ICRDICCT`25; ISBN 978-989-758-777-1, SciTePress, pages 39-44. DOI: 10.5220/0013922100004919

in Bibtex Style

@conference{icrdicct`2525,
author={R. Ravindraiah and Bhupalam Deeraj and Ammaladinne Reddy and Manchineella Manikanta},
title={Advancing Digital Design: Reversible Pipelined ALU Synthesis for Efficient RTL Logic},
booktitle={Proceedings of the 1st International Conference on Research and Development in Information, Communication, and Computing Technologies - ICRDICCT`25},
year={2025},
pages={39-44},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0013922100004919},
isbn={978-989-758-777-1},
}

in EndNote Style

TY - CONF

JO - Proceedings of the 1st International Conference on Research and Development in Information, Communication, and Computing Technologies - ICRDICCT`25
TI - Advancing Digital Design: Reversible Pipelined ALU Synthesis for Efficient RTL Logic
SN - 978-989-758-777-1
AU - Ravindraiah R.
AU - Deeraj B.
AU - Reddy A.
AU - Manikanta M.
PY - 2025
SP - 39
EP - 44
DO - 10.5220/0013922100004919
PB - SciTePress