Development and Validation of a High-Performance Network-On-Chip Architecture with Wireless Sensor Network Controls

P. Arivazhagi, A. Ruccaiyatasleema, D. Jayalakshmi

2025

Abstract

Wireless Sensor Networks (WSNs) are increasingly integral to numerous IoT applications, such as environmental monitoring, healthcare, and smart cities. However, one of the primary challenges in WSNs is ensuring energy efficiency and high performance, particularly when nodes are constrained by limited battery life or energy-harvesting capabilities. This paper introduces a novel 32-bit accumulator-based System-on-Chip (SoC) design aimed at optimizing data processing and power consumption in WSN nodes. The design integrates a configurable Look-Up Table (LUT)-based stacking mechanism that adapts the sensor data flow in real time, enhancing the system's flexibility and computational efficiency. The system's power consumption is minimized while maintaining high data throughput, making it suitable for dynamic, resource-constrained environments. To further improve the system's performance, the Whale Optimization Algorithm (WOA), inspired by the hunting techniques of humpback whales, is employed to optimize key network parameters, such as node placement, data routing, and energy allocation. The proposed system's simulation results demonstrate significant improvements in energy efficiency and real-time data processing, offering a viable solution for WSNs in both small- and large-scale applications.

Paper Citation

in Harvard Style

Arivazhagi P., Ruccaiyatasleema A. and Jayalakshmi D. (2025). Development and Validation of a High-Performance Network-On-Chip Architecture with Wireless Sensor Network Controls. In Proceedings of the 1st International Conference on Research and Development in Information, Communication, and Computing Technologies - ICRDICCT`25; ISBN 978-989-758-777-1, SciTePress, pages 823-832. DOI: 10.5220/0013890500004919

in Bibtex Style

@conference{icrdicct`2525,
author={P. Arivazhagi and A. Ruccaiyatasleema and D. Jayalakshmi},
title={Development and Validation of a High-Performance Network-On-Chip Architecture with Wireless Sensor Network Controls},
booktitle={Proceedings of the 1st International Conference on Research and Development in Information, Communication, and Computing Technologies - ICRDICCT`25},
year={2025},
pages={823-832},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0013890500004919},
isbn={978-989-758-777-1},
}

in EndNote Style

TY - CONF

JO - Proceedings of the 1st International Conference on Research and Development in Information, Communication, and Computing Technologies - ICRDICCT`25
TI - Development and Validation of a High-Performance Network-On-Chip Architecture with Wireless Sensor Network Controls
SN - 978-989-758-777-1
AU - Arivazhagi P.
AU - Ruccaiyatasleema A.
AU - Jayalakshmi D.
PY - 2025
SP - 823
EP - 832
DO - 10.5220/0013890500004919
PB - SciTePress