Efficient Three Operand Adder Design with Carry Prefix Logic for Reduced Delay

S. Divya, M. Mohankumar, J. Dhanasekar, R. Krishnaraj, T. Senthil, Vikram N.

2025

Abstract

Cryptography and pseudorandom number generators are essential tools from the modern digital world. For performance improvement adder implementations like (CS3A) and (HCA) are frequently employed. But these adders exhibit high propagation delays that reduce the efficiency of the system. A new three-operand binary adder architecture is presented that utilizes carry-prefix logic to achieve low power and propagation delay. The design below obtains a log₂n time complexity via pre-computed bitwise addition, followed by a carry-prefix compute. The proposed design was implemented with Xilinx ISE 14.7, showing that it is power efficient and less delay-centric than CS3A and HCA adders. These results attest to the fact that the proposed architecture can be utilized to enhance the performance of a digital system.

Paper Citation

in Harvard Style

Divya S., Mohankumar M., Dhanasekar J., Krishnaraj R., Senthil T. and N. V. (2025). Efficient Three Operand Adder Design with Carry Prefix Logic for Reduced Delay. In Proceedings of the 1st International Conference on Research and Development in Information, Communication, and Computing Technologies - ICRDICCT`25; ISBN 978-989-758-777-1, SciTePress, pages 795-799. DOI: 10.5220/0013890100004919

in Bibtex Style

@conference{icrdicct`2525,
author={S. Divya and M. Mohankumar and J. Dhanasekar and R. Krishnaraj and T. Senthil and Vikram N.},
title={Efficient Three Operand Adder Design with Carry Prefix Logic for Reduced Delay},
booktitle={Proceedings of the 1st International Conference on Research and Development in Information, Communication, and Computing Technologies - ICRDICCT`25},
year={2025},
pages={795-799},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0013890100004919},
isbn={978-989-758-777-1},
}

in EndNote Style

TY - CONF

JO - Proceedings of the 1st International Conference on Research and Development in Information, Communication, and Computing Technologies - ICRDICCT`25
TI - Efficient Three Operand Adder Design with Carry Prefix Logic for Reduced Delay
SN - 978-989-758-777-1
AU - Divya S.
AU - Mohankumar M.
AU - Dhanasekar J.
AU - Krishnaraj R.
AU - Senthil T.
AU - N. V.
PY - 2025
SP - 795
EP - 799
DO - 10.5220/0013890100004919
PB - SciTePress