Machine Learning-Based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores

Stefano Ribes, Fabio Malatesta, Grazia Garzo, Alessandro Palumbo

2024

Abstract

Hardware Trojans (HTs) pose a severe threat to integrated circuits, potentially compromising electronic devices, exposing sensitive data, or inducing malfunction. Detecting such malicious modifications is particularly challenging in complex systems and commercial CPUs, where they can occur at various design stages, from initial HDL coding to the final hardware implementation. This paper introduces a machine learning-based strategy for the detection and classification of HTs within RISC-V soft cores implemented in Field-Programmable Gate Arrays (FPGAs). Our approach comprises a systematic methodology for comprehensive data collection and estimation from FPGA bitstreams, enabling us to extract insights ranging from hardware performance counters to intricate metrics like design clock frequency and power consumption. Our ML models achieve perfect accuracy scores when analyzing features related to both synthesis, implementation results, and performance counters. We also address the challenge of identifying HTs solely through performance counters, highlighting the limitations of this approach. Additionally, our work emphasizes the significance of Implementation Features (IFs), particularly circuit timing, in achieving high accuracy in HT detection.

Paper Citation

in Harvard Style

Ribes S., Malatesta F., Garzo G. and Palumbo A. (2024). Machine Learning-Based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores. In Proceedings of the 10th International Conference on Information Systems Security and Privacy - Volume 1: ICISSP; ISBN 978-989-758-683-5, SciTePress, pages 717-724. DOI: 10.5220/0012324200003648

in Bibtex Style

@conference{icissp24,
author={Stefano Ribes and Fabio Malatesta and Grazia Garzo and Alessandro Palumbo},
title={Machine Learning-Based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores},
booktitle={Proceedings of the 10th International Conference on Information Systems Security and Privacy - Volume 1: ICISSP},
year={2024},
pages={717-724},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0012324200003648},
isbn={978-989-758-683-5},
}

in EndNote Style

TY - CONF

JO - Proceedings of the 10th International Conference on Information Systems Security and Privacy - Volume 1: ICISSP
TI - Machine Learning-Based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores
SN - 978-989-758-683-5
AU - Ribes S.
AU - Malatesta F.
AU - Garzo G.
AU - Palumbo A.
PY - 2024
SP - 717
EP - 724
DO - 10.5220/0012324200003648
PB - SciTePress