PHASE LOCKED LOOPS DESIGN AND ANALYSIS

Nikolay V. Kuznetsov, Gennady A. Leonov, Svetlana S. Seledzhi

2008

Abstract

New methods, for the design of different block diagrams of PLL, using the asymphtotic analysis of high-frequency periodic oscillations, are suggested. The PLL description on three levels is made: 1) on the level of electronic realizations; 2) on the level of phase and frequency relations between inputs and outputs in block diagrams; 3) on the level of differential and integro-differential equations. On the base of such description, the block diagram of floating PLL for the elimination of clock skew and that of frequency synthesizer is proposed. The rigorous mathematical formulation of the Costas loop for the clock oscillators are first obtained. The theorem on a PLL global stability is proved.

References

  1. Abramovitch, D., 2002. Phase-Locked Loope A control Centric. Tutorial, in the Proceedings of the 2002 ACC.
  2. Aleksenko, A., 2004. Digital engineering, Unimedstyle. Moscow. (in Russian)
  3. Best Ronald E., 2003. Phase-Lock Loops: Design, Simulation and Application, McGraw Hill, 5ed.
  4. Egan, W.F., 2000. Frequency Synthesis by Phase Lock ,(2nd ed.), John Wiley and Sons, 2ed.
  5. Gardner F., 2005. Phase-lock techniques, John Wiley & Sons, New York, 2ed.
  6. Kroupa, V., 2003. Phase Lock Loops and Frequency Synthesis, John Wiley & Sons.
  7. Kung, S., 1988. VLSI Array Processors, Prentice Hall. New York.
  8. Lapsley, P., Bier, J., Shoham, A., Lee, E., 1997. DSP Processor Fundamentals Architecture and Features, IEE Press. New York.
  9. Leonov, G., Reitmann, V., Smirnova, V., 1992. Nonlocal Methods for Pendulum-Like Feedback Systems, Teubner Verlagsgesselschaft. Stuttgart; Leipzig.
  10. Leonov, G., Ponomarenko, D., Smirnova, V., 1996. Frequency-Domain Methods for Nonlinear Analysis. Theory and Applications, World Scientific. Singapore.
  11. Leonov, G., Seledzhi, S., 2002. Phase locked loops in array processors, Nevsky dialekt. St.Petersburg. (in Russian)
  12. Lindsey, W., 1972, Sinchronization systems in communication and ontrol, Prentice-Hall. New Jersey.
  13. Lindsey, W., Chie, C., 1981. A Survey of Digital Phase Locked Loops. Proceedings of the IEEE.
  14. Razavi, B., 2003. Phase-Locking in High-Performance Systems: From Devices to Architectures, John Wiley & Sons.
  15. Smith, S., 1999. The Scientist and Engineers Guide to Digital Dignal Processing, California Technical Publishing. San Diego.
  16. Solonina, A., Ulahovich, D., Jakovlev, L., 2000. The Motorola Digital Signal Processors. BHV, St. Petersburg. (in Russian)
  17. Ugrumov, E., 2000. Digital St.Petersburg. (in Russian)
  18. Viterbi, A., 1966. Principles of coherent communications, McGraw-Hill. New York.
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Paper Citation


in Harvard Style

Kuznetsov N., Leonov G. and Seledzhi S. (2008). PHASE LOCKED LOOPS DESIGN AND ANALYSIS . In Proceedings of the Fifth International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO, ISBN 978-989-8111-32-6, pages 114-118. DOI: 10.5220/0001485401140118


in Bibtex Style

@conference{icinco08,
author={Nikolay V. Kuznetsov and Gennady A. Leonov and Svetlana S. Seledzhi},
title={PHASE LOCKED LOOPS DESIGN AND ANALYSIS},
booktitle={Proceedings of the Fifth International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO,},
year={2008},
pages={114-118},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0001485401140118},
isbn={978-989-8111-32-6},
}


in EndNote Style

TY - CONF
JO - Proceedings of the Fifth International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO,
TI - PHASE LOCKED LOOPS DESIGN AND ANALYSIS
SN - 978-989-8111-32-6
AU - Kuznetsov N.
AU - Leonov G.
AU - Seledzhi S.
PY - 2008
SP - 114
EP - 118
DO - 10.5220/0001485401140118