A 16-BIT SWITCHED-CAPACITOR SIGMA-DELTA
MODULATOR MATLAB MODEL EXPLOITING TWO-STEP
QUANTIZATION PROCESS
Lukas Fujcik, Radimir Vrba
Faculty of Electrical Engineering and Communication, Brno University of Technology, Udolni 53, Brno, Czech Republic
Miroslav Sveda
Faculty of Information Technology, Brno University of Technology, Bozetechova 2, Brno, Czech Republic
Keywords: Sigma-delta modulator, switched-capacitor technology, quatization process.
Abstract: This paper presents a novel architecture of high-order single-stage sigma-delta (ΣΔ) converter for sensor
measurement. The two-step quantization technique was utilized to design a novel architecture of ΣΔ
modulator. The time steps are interleaved to achieve resolution improvement without decreasing of
conversion speed. This technique can be useful for low oversampling ratio. The novel architecture was
designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. The
proposed architecture of switched-capacitor (SC) ΣΔ modulator was simulated with blocks containing
nonidealities, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc
gain, finite bandwidth, slew rate and saturation voltages). The novel architecture of SC ΣΔ modulator with
two-step quantization process was designed and simulated in MATLAB SIMULINK.
1 INTRODUCTION
High-resolution analog-to-digital conversion based
on Σ∆ modulation has become commonplace in
many measurement applications including audio,
seismic, biomedical and harsh environment sensing.
Σ∆ methods incorporating oversampling and noise
shaping provide improved resolution over Nyquist-
rate conversion methods by trading component
accuracy for time. However, this AD converter
architecture requires both filtering and
downsampling of the oversampled signal, or
decimation filtering (Norsworthy et al., 1997).
The ΣΔ modulation relies on oversampling, which
means that all operations, like an integration AD and
DA conversion, have to be performed within
roughly the same time. If any operation takes
significantly longer time than others, it will limit the
speed, and consequently dynamic range. ΣΔ
modulators can be implemented either with
continuous-time or with sampled-data techniques.
The most popular approach is based on a sampled-
data solution with SC implementation. For this
reason, we will focus on the case of SC modulators
in this paper. In fact, SC modulators can be
efficiently realized in standard CMOS technology
and included in complete mixed-signal systems
without any performance degradation.
In the design of a high-performance SC
modulator, two main issues have to be addressed by
the designers.
1) Which is the best architecture to fulfill the
application requirements?
2) For a given architecture, which are the
requirements for the building blocks?
2 MODULATOR TOPOLOGY
Proposed Architecture. New proposed architecture
of sigma-delta modulator is derived from CIDIDF
second order sigma-delta modulator (Fig. 1).
Multibit ΣΔ modulator with two-step quantization
process (Fig. 2) is based on dividing the AD
142
Fujcik L., Vrba R. and Sveda M. (2006).
A 16-BIT SWITCHED-CAPACITOR SIGMA-DELTA MODULATOR MATLAB MODEL EXPLOITING TWO-STEP QUANTIZATION PROCESS.
In Proceedings of the Third International Conference on Informatics in Control, Automation and Robotics, pages 142-147
DOI: 10.5220/0001207901420147
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