Authors:
Ji Gu
and
Tohru Ishihara
Affiliation:
Kyoto University, Japan
Keyword(s):
Energy Efficiency, Optimization Techniques, Microprocessor, Multitasking, Embedded Systems.
Related
Ontology
Subjects/Areas/Topics:
Data Communication Networking
;
Energy and Economy
;
Energy-Aware Systems and Technologies
;
Optimization Techniques for Efficient Energy Consumption
;
Performance Evaluation
;
Software Engineering
;
Software Project Management
;
Telecommunications
Abstract:
Microprocessors increasingly execute multiple tasks in step with the increasing complexity of modern embedded
applications. Shared by multiple tasks, conventional on-chip L1 instruction cache (I-cache) usually suffers
a high cache miss ratio due to inter/intra task interferences and is the most energy-consuming component of
the processor chip. This paper presents a power-efficient loop instruction cache design for multitasking embedded
applications, which is a two-fold technique that can significantly reduce the L1 I-cache accesses for
energy saving and reduce the I-cache misses caused by task interference. Experiments on a case study show
that our scheme reduces energy consumption in the I-cache hierarchy by 36.5% and I-cache misses can be
reduced from 6.0% to 18.3%, depending on the frequency of context switch in the multitasking system.