Authors:
Dariusz Kościelnik
and
Marek Miśkowicz
Affiliation:
AGH University of Science and Technology, Poland
Keyword(s):
Asynchronous circuits, Analog-to-digital converters, Asynchronous Sigma-Delta modulation.
Related
Ontology
Subjects/Areas/Topics:
Adaptive Signal Processing and Control
;
Informatics in Control, Automation and Robotics
;
Nonlinear Signals and Systems
;
Signal Processing, Sensors, Systems Modeling and Control
;
Signal Reconstruction
Abstract:
A challenging problem of today’s ADC design is a development of low voltage, low power and possibly high performance converters. The ever growing demand for decreasing the supply voltage of semiconductor devices due to scaling the feature size of VLSI technology has pushed the design of analog integrated circuit to its limits. The same problem concerns the analog-to-digital converters since lowering supply voltage results in a reduction of a voltage increment corresponding to the least significant bit (LSB) in signal amplitude quantization. In the paper, an important alternative to conventional ADCs is presented. To overcome problems with decreasing accuracy of amplitude quantization, a new class of asynchronous ADCs is discussed where the mapping of an analog signal into time domain rather than into amplitude domain is used. The asynchronous ADCs are not controlled by any global clock but self-timed. The local reference clock is used only to quantize time intervals that represent th
e converted signal amplitude. The design of asynchronous Sigma-Delta analog-to-digital converter (ASD-ADC) with serial output interface is discussed in details. The ASD-ADC together with the loss-free asynchronous analog signal recovery method developed recently provides possibility to establish the asynchronous digital signal processing chain.
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