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Authors: Josefa Díaz 1 ; Francisco Fernández de Vega 1 ; J. Ignacio Hidalgo 2 and Oscar Garnica 2

Affiliations: 1 University of Extremadura, Spain ; 2 Universidad Complutense de Madrid, Spain

ISBN: 978-989-8425-31-7

Keyword(s): Genetic algorithms, Simultaneous multithreading, Optimization, Parisian approach.

Related Ontology Subjects/Areas/Topics: Artificial Intelligence ; Computational Intelligence ; Evolutionary Computing ; Genetic Algorithms ; Informatics in Control, Automation and Robotics ; Intelligent Control Systems and Optimization ; Soft Computing

Abstract: Evolutionay Algorithm are techniques widely used in the resolution of complex problems. On the other hand, Simultaneous Multithreading improves the throughput of the processor core taking advantage of Instruction Level Parallelism and Thread Level Parallelism. In this environment adaptation the cache configuration, at runtime according to workloads settings will be improved the processor performance. This improvement is achieved by using resizable caches. In a previous work, we proposed a Genetic Algorithm to find the better cache configurations according to the needs and characteristics of the workloads. However the computational cost needed for the evaluation process is very high. In this paper we propose the use of the Parisian Evolution Approach to improve dynamically reconfigurable cache designs, and reduce the computational cost associated. We study the behavior of a set of benchmarks, taking into account their needs over cache memory hierarchy in each phase of execution, in ord er to adapt the cache configuration and to increase the number of instructions per cycle. Experimental results show a large saving in computing time and some improvement on the instructions per cycle achieved in previous approaches. (More)

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Paper citation in several formats:
Díaz, J.; Fernández de Vega, F.; Ignacio Hidalgo, J. and Garnica, O. (2010). PARISIAN APPROACH - Reducing Computational Effort to Improve SMT Performance by setting Resizable Caches.In Proceedings of the International Conference on Evolutionary Computation - Volume 1: ICEC, (IJCCI 2010) ISBN 978-989-8425-31-7, pages 275-280. DOI: 10.5220/0003113702750280

@conference{icec10,
author={Josefa Díaz. and Francisco Fernández de Vega. and J. Ignacio Hidalgo. and Oscar Garnica.},
title={PARISIAN APPROACH - Reducing Computational Effort to Improve SMT Performance by setting Resizable Caches},
booktitle={Proceedings of the International Conference on Evolutionary Computation - Volume 1: ICEC, (IJCCI 2010)},
year={2010},
pages={275-280},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003113702750280},
isbn={978-989-8425-31-7},
}

TY - CONF

JO - Proceedings of the International Conference on Evolutionary Computation - Volume 1: ICEC, (IJCCI 2010)
TI - PARISIAN APPROACH - Reducing Computational Effort to Improve SMT Performance by setting Resizable Caches
SN - 978-989-8425-31-7
AU - Díaz, J.
AU - Fernández de Vega, F.
AU - Ignacio Hidalgo, J.
AU - Garnica, O.
PY - 2010
SP - 275
EP - 280
DO - 10.5220/0003113702750280

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