Author:
Karthik Mahesh Varadarajan
Affiliation:
ACIN and Technical University of Vienna, Austria
Keyword(s):
Constant divider circuit, Integer division, Serial division, Full-precision division, DSP, VLSI, Computational optimization.
Related
Ontology
Subjects/Areas/Topics:
Av-Communication and Multimedia
;
Digital Signal Processing
;
Embedded Communications Systems
;
Image and Multidimensional Signal Processing
;
Pervasive Embedded Devices
;
Real-Time Systems
;
Software Architectures
;
Telecommunications
Abstract:
Implementation specific computation modules hold the key to the success of fast DSP and Embedded systems. Exponential encoders, dedicated multipliers, barrel shifters and accumulators are common units available on DSPs. The family of constant divider circuits of the form 2p±1, which are useful for image processing, statistical processing like histograms etc., is the specific focus of this paper. This family is largely dominated by the Residue Number System (RNS), Petry and Srinivasan algorithms and the Shuo-Yen Robert-Li algorithm. While these algorithms offer various trade-offs in terms of accuracy, memory footprint, power consumption and timing behavior, none of these methods are suited for processing serialized inputs, dividend inputs with apriori unknown bit length and the circuits have to be replaced with change in input bit length. The circuit size also grows enormously for large input lengths along with a reduction in accuracy. These methods are suited only for integer divisio
n and are unsuited for extension to floating/fixed point division. In this paper a novel constant divider algorithm is offered, which overcomes the above mentioned limitations while handling arbitrary length, serial/ parallel data and producing full-precision, full-accuracy, floating point capable results with constant circuit requirements and comparable timing to state of the art methods.
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