Authors:
A. Shahrabi
and
A. Ahmadinia
Affiliation:
Glasgow Caledonian University, United Kingdom
Keyword(s):
Network-on-Chip, Router Architecture, Low Power Design, Performance Evaluation.
Related
Ontology
Subjects/Areas/Topics:
Embedded Communications Systems
;
Telecommunications
;
VLSI Design and Implementation
Abstract:
Efficient buffer management is not only instrumental in the overall performance of the on-chip networks but also greatly affects the network energy consumption. In fact, any improvement or deterioration of network performance and energy budget is the net result of increasing buffer utilisation (storing blocked flits) and reducing buffer utilisation (delivering buffered flits). In order to improve the network performance and efficiently utilising the available routers buffer space in NoCs, a new router architecture, called Pool-Buffering (PB), is proposed in this paper. By exploiting a flexible ring buffer structure, the buffer space of the proposed architecture is shared amongst all input channels; allocating more buffer to the busy input channels and less to the idle ones. Implementation results show up to 50% in reducing power consumption when compared to a traditional router. Moreover, our extensive simulation study shows that the proposed router architecture enhances the network
performance by increasing the acceptance traffic rate and decreasing the average message latency.
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