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High-level Performance Evaluation of Object Detection based on Massively Parallel Focal-plane Acceleration Requiring Minimum Pixel Area Overhead

Topics: Camera Networks and Vision; Features Extraction; Image Formation, Acquisition Devices and Sensors; Image Generation Pipeline: Algorithms and Techniques; Object Detection and Localization; Pervasive Smart Cameras

Authors: Eloy Parra-Barrero 1 ; Jorge Fernández-Berni 2 ; Fernanda D. V. R. Oliveira 3 ; Ricardo Carmona-Galán 2 and Ángel Rodríguez-Vázquez 2

Affiliations: 1 Universidad de Sevilla, Spain ; 2 Instituto de Microelectrónica de Sevilla (IMSE-CNM) and CSIC-Universidad de Sevilla, Spain ; 3 Universidade Federal do Rio de Janeiro, Brazil

ISBN: 978-989-758-175-5

Keyword(s): Embedded Systems, Vision Pipeline, Early Vision, Smart Image Sensors, Vision Chips, Focal-plane Processing, Object Detection, Viola-Jones Algorithm, Performance, Processing Acceleration.

Related Ontology Subjects/Areas/Topics: Applications and Services ; Camera Networks and Vision ; Computer Vision, Visualization and Computer Graphics ; Features Extraction ; Image and Video Analysis ; Image Formation and Preprocessing ; Image Formation, Acquisition Devices and Sensors ; Image Generation Pipeline: Algorithms and Techniques ; Pervasive Smart Cameras

Abstract: Smart CMOS image sensors can leverage the inherent data-level parallelism and regular computational flow of early vision by incorporating elementary processors at pixel level. However, it comes at the cost of extra area having a strong impact on the sensor sensitivity, resolution and image quality. In this scenario, the fundamental challenge is to devise new strategies capable of boosting the performance of the targeted vision pipeline while minimally affecting the sensing function itself. Such strategies must also feature enough flexibility to accommodate particular application requirements. From these high-level specifications, we propose a focal-plane processing architecture tailored to speed up object detection via the Viola-Jones algorithm. This architecture is supported by only two extra transistors per pixel and simple peripheral digital circuitry that jointly make up a massively parallel reconfigurable processing lattice. A performance evaluation of the proposed scheme in term s of accuracy and acceleration for face detection is reported. (More)

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Paper citation in several formats:
Parra-Barrero, E.; Fernández-Berni, J.; Oliveira, F.; Carmona-Galán, R. and Rodríguez-Vázquez, Á. (2016). High-level Performance Evaluation of Object Detection based on Massively Parallel Focal-plane Acceleration Requiring Minimum Pixel Area Overhead.In Proceedings of the 11th Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications - Volume 3: VISAPP, (VISIGRAPP 2016) ISBN 978-989-758-175-5, pages 79-85. DOI: 10.5220/0005651200790085

@conference{visapp16,
author={Eloy Parra{-}Barrero. and Jorge Fernández{-}Berni. and Fernanda D. V. R. Oliveira. and Ricardo Carmona{-}Galán. and Ángel Rodríguez{-}Vázquez.},
title={High-level Performance Evaluation of Object Detection based on Massively Parallel Focal-plane Acceleration Requiring Minimum Pixel Area Overhead},
booktitle={Proceedings of the 11th Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications - Volume 3: VISAPP, (VISIGRAPP 2016)},
year={2016},
pages={79-85},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0005651200790085},
isbn={978-989-758-175-5},
}

TY - CONF

JO - Proceedings of the 11th Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications - Volume 3: VISAPP, (VISIGRAPP 2016)
TI - High-level Performance Evaluation of Object Detection based on Massively Parallel Focal-plane Acceleration Requiring Minimum Pixel Area Overhead
SN - 978-989-758-175-5
AU - Parra-Barrero, E.
AU - Fernández-Berni, J.
AU - Oliveira, F.
AU - Carmona-Galán, R.
AU - Rodríguez-Vázquez, Á.
PY - 2016
SP - 79
EP - 85
DO - 10.5220/0005651200790085

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