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ON-CHIP FLUORESCENCE LIFETIME EXTRACTION USING SYNCHRONOUS GATING SCHEME - Theoretical Error Analysis and Practical Implementation

Topics: Laser and Opto-Electronics Signal Processing Applications; Medical Image Detection, Acquisition, Analysis and Processing; Medical Signal Acquisition, Analysis and Processing; Real-Time Systems; Time and Frequency Response

Authors: Day-Uei Li 1 ; Bruce Rae 1 ; David Renshaw 1 ; Robert Henderson 1 and Eleanor Bonnist 2

Affiliations: 1 Institute for Integrated Micro and Nano Systems, The University of Edinburgh, United Kingdom ; 2 School of Chemistry and the Collaborative Optical SpectroscopyMicromanipulation and Imaging Centre (COSMIC), University of Edinburgh, United Kingdom

Keyword(s): Fluorescence lifetime imaging microscopy (FLIM). Error analysis. On-chip implementation. Rapid lifetime determination (RLD). Single photon avalanche diode (SPAD). Time-correlated single-photon counting (TCSPC). Data fitting. Pipe-lined RLD. Instrumental response function (IRF).

Related Ontology Subjects/Areas/Topics: Applications and Services ; Biomedical Engineering ; Biomedical Signal Processing ; Computer Vision, Visualization and Computer Graphics ; Informatics in Control, Automation and Robotics ; Laser and Opto-Electronics Signal Processing Applications ; Medical Image Detection, Acquisition, Analysis and Processing ; Real-Time Systems ; Signal Processing, Sensors, Systems Modeling and Control ; Time and Frequency Response ; Time-Frequency Analysis

Abstract: A synchronous gating technique was proposed for fluorescent photon collecting. The two- and multi-gate rapid lifetime determination (RLD) technique was applied to implement on-chip fluorescence lifetime extraction. Compared with all available iterative least square method (LSM) or maximum likelihood estimation (MLE) based general purpose FLIM analysis software, we offer a method for the direct calculation of lifetime based on the photon counts stored in on-chip memory and deliver faster analysis to enable real-time applications. Theoretical error analysis of the two-gate RLD technique was derived for comparison. The performance of the algorithms were tested on a single-exponential histogram obtained from a CMOS SPAD detector chip using a 468nm laser diode light source with optimized gate width. Moreover, a multi-exponential pipelined RLD FLIM technique was also proposed and tested on a four- exponential decay DNA sample containing a single adenine analogue 2-aminopurine.

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Paper citation in several formats:
Li, D.; Rae, B.; Renshaw, D.; Henderson, R. and Bonnist, E. (2008). ON-CHIP FLUORESCENCE LIFETIME EXTRACTION USING SYNCHRONOUS GATING SCHEME - Theoretical Error Analysis and Practical Implementation. In Proceedings of the First International Conference on Bio-inspired Systems and Signal Processing (BIOSTEC 2008) - Volume 2: BIOSIGNALS; ISBN 978-989-8111-18-0; ISSN 2184-4305, SciTePress, pages 171-176. DOI: 10.5220/0001061301710176

@conference{biosignals08,
author={Day{-}Uei Li. and Bruce Rae. and David Renshaw. and Robert Henderson. and Eleanor Bonnist.},
title={ON-CHIP FLUORESCENCE LIFETIME EXTRACTION USING SYNCHRONOUS GATING SCHEME - Theoretical Error Analysis and Practical Implementation},
booktitle={Proceedings of the First International Conference on Bio-inspired Systems and Signal Processing (BIOSTEC 2008) - Volume 2: BIOSIGNALS},
year={2008},
pages={171-176},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0001061301710176},
isbn={978-989-8111-18-0},
issn={2184-4305},
}

TY - CONF

JO - Proceedings of the First International Conference on Bio-inspired Systems and Signal Processing (BIOSTEC 2008) - Volume 2: BIOSIGNALS
TI - ON-CHIP FLUORESCENCE LIFETIME EXTRACTION USING SYNCHRONOUS GATING SCHEME - Theoretical Error Analysis and Practical Implementation
SN - 978-989-8111-18-0
IS - 2184-4305
AU - Li, D.
AU - Rae, B.
AU - Renshaw, D.
AU - Henderson, R.
AU - Bonnist, E.
PY - 2008
SP - 171
EP - 176
DO - 10.5220/0001061301710176
PB - SciTePress