A Workflow Model For Integrating IC Design and Testing

Andres Mellik

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Paper

A Workflow Model For Integrating IC Design and Testing

In Proceedings of the 2nd International Workshop on Computer Supported Activity Coordination - Volume 0ICEIS, 103-108, 2005 , Miami, United States

Author: Andres Mellik

Affiliation: Tallinn University of Technology, Estonia

Abstract: This paper outlines the challenges facing the domain of automated testing of mixed-signal integrated circuits and how these can be tackled by enhancing communication between the design and test engineers. An abstract workflow model is introduced for seem-less interaction of design and test teams, thus enabling faster work-flow and a greater redundancy in the correctness of communicated specification data. The latter is embedded into a system-level model and completely integrated into the process. A data-sheet integration methodology is briefly introduced with several application-level requirements and integration guidelines. The goal is to reduce the time for developing and running test programs, which is a major cost factor in the reducing life-cycles of mixed-signal devices. The paper emphasizes obstacles in current settings and suggests workarounds.

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Paper citation in several formats:

Mellik, A. (2005). A Workflow Model For Integrating IC Design and Testing. In Proceedings of the 2nd International Workshop on Computer Supported Activity Coordination (ICEIS 2005) - CSAC; ISBN 972-8865-21-X, SciTePress, pages 103-108. DOI: 10.5220/0002558901030108

@conference{csac05,
author={Andres Mellik.},
title={A Workflow Model For Integrating IC Design and Testing},
booktitle={Proceedings of the 2nd International Workshop on Computer Supported Activity Coordination (ICEIS 2005) - CSAC},
year={2005},
pages={103-108},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0002558901030108},
isbn={972-8865-21-X},
}

TY - CONF

JO - Proceedings of the 2nd International Workshop on Computer Supported Activity Coordination (ICEIS 2005) - CSAC
TI - A Workflow Model For Integrating IC Design and Testing
SN - 972-8865-21-X
AU - Mellik, A.
PY - 2005
SP - 103
EP - 108
DO - 10.5220/0002558901030108
PB - SciTePress