Authors:
Jesús Miguel Pérez Llano
and
Víctor Fernández Solórzano
Affiliation:
Microelectronics Engineering Group TEISA, ETSIIyT, Cantabria University, Spain
Keyword(s):
LDPC, eIRA, DVB-S2, BIBD, error floor.
Related
Ontology
Subjects/Areas/Topics:
Channel Coding, Modulation and Multi-User Detection
;
Detection, Decoding and Diversity Techniques
;
Telecommunications
;
Wireless Information Networks and Systems
Abstract:
This paper describes a method based on hierarchical matrices and primitive generators that allows low cost coder and decoder implementations. The hierarchical approach is well suited for decoder implementation and, in addition, the method has been applied to eIRA structures which have demonstrated a reduced coder implementation complexity. Despite the added structure to eIRA original codes, the architecture presented shows similar BER performance. To achieve this, BIBDs have been used to avoid length-four cycles and primimitive generators contribute to get a pseudo-random construction. Moreover, the reduction of low weight codewords and near codewords are considered in order to reduce error-floors.