DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA

Sumedh Attarde, Siddharth Joshi, Yash Deshpande, Sunil Puranik, Sachin Patkar

2011

Abstract

In this paper, we present the design of an embedded system performing double precision sparse matrix vector multiplication (SpMxV), a key scientific computation kernel in iterative solvers, for very large matrices (millions of rows). The embedded system is implemented using the Xilinx MicroBlaze platform on the XUPV5-LX110T FPGA development board. Due to their size, matrices generally encountered in scientific computation need to be stored on off-chip DRAMs. A novel processing paradigm involving blocking of the matrix, and a novel data access mechanism which pre-fetches required data in bursts from off-chip DRAMS to hide large DRAM random access latencies are proposed and implemented. The processing element has been implemented as a prototype accelerator peripheral in an embedded system for the iterative Gauss-Jacobi algorithm.

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Paper Citation


in Harvard Style

Attarde S., Joshi S., Deshpande Y., Puranik S. and Patkar S. (2011). DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA . In Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS, ISBN 978-989-8425-48-5, pages 476-484. DOI: 10.5220/0003400804760484


in Harvard Style

Attarde S., Joshi S., Deshpande Y., Puranik S. and Patkar S. (2011). DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA . In Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS, ISBN 978-989-8425-48-5, pages 476-484. DOI: 10.5220/0003400804760484


in Bibtex Style

@conference{peccs11,
author={Sumedh Attarde and Siddharth Joshi and Yash Deshpande and Sunil Puranik and Sachin Patkar},
title={DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA},
booktitle={Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,},
year={2011},
pages={476-484},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003400804760484},
isbn={978-989-8425-48-5},
}


in Bibtex Style

@conference{peccs11,
author={Sumedh Attarde and Siddharth Joshi and Yash Deshpande and Sunil Puranik and Sachin Patkar},
title={DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA},
booktitle={Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,},
year={2011},
pages={476-484},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003400804760484},
isbn={978-989-8425-48-5},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,
TI - DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA
SN - 978-989-8425-48-5
AU - Attarde S.
AU - Joshi S.
AU - Deshpande Y.
AU - Puranik S.
AU - Patkar S.
PY - 2011
SP - 476
EP - 484
DO - 10.5220/0003400804760484


in EndNote Style

TY - CONF
JO - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,
TI - DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA
SN - 978-989-8425-48-5
AU - Attarde S.
AU - Joshi S.
AU - Deshpande Y.
AU - Puranik S.
AU - Patkar S.
PY - 2011
SP - 476
EP - 484
DO - 10.5220/0003400804760484