HIERARCHICAL AGENT MONITORING DESIGN PLATFORM - Towards Self-aware and Adaptive Embedded Systems

Liang Guang, Bo Yang, Juha Plosila, Jouni Isoaho, Hannu Tenhunen

Abstract

Hierarchical agent monitoring design platform (HAM) is presented as a generic design approach for the emerging self-aware and adaptive embedded systems. Such systems, with various existing proposals for different advanced features, call for a concrete, practical and portable design approach. HAM addresses this necessity by providing a scalable and generically applicable design platform. This paper elaborately describes the hierarchical agent monitoring architecture, with extensive reference to the state-of-the-art technology in embedded systems. Two case studies are exemplified to demonstrate the design process and benefits of HAM design platform. One is about hierarchical agent monitored Network-on-Chip with quantitative experiments of hierarchical energy management. The other one is a projectional study of applying HAM on smart house systems, focusing on the design for enhanced dependability.

References

  1. Al Faruque, M. A., Krist, R., and Henkel, J. (2008). Adam: run-time agent-based distributed application mapping for on-chip communication. In DAC 7808: Proceedings of the 45th annual Design Automation Conference, pages 760-765, New York, NY, USA. ACM.
  2. Guang, L. and Jantsch, A. (2006). Adaptive power management for the on-chip communication network. In Proc. of Euromicro DSD'06, pages 649-656.
  3. Guang, L., Plosila, J., Isoaho, J., and Tenhunen, H. (2010). Hierarchical agent monitored parallel on-chip system: A novel design paradigm and its formal specification. International Journal of Embedded and Real-Time communication Systems (IJERTCS), 1(2):86-105.
  4. Helal, S., Mann, W., El-Zabadani, H., King, J., Kaddoura, Y., and Jansen, E. (2005). The gator tech smart house: A programmable pervasive space. Computer, 38:50- 60.
  5. Horn, P. (2001). Autonomic computing: Ibm's perspective on the state of information technology. online.
  6. Hu, J. and Marculescu, R. (2005). Energy and performanceaware mapping for regular noc architectures. IEEE Transactions on CAD, 24(4):551-562.
  7. Jantsch, A. and Tenhunen, H. (2003). Networks on Chip. Kluwer Academic Publishers.
  8. Kahng, A., Li, B., Peh, L.-S., and Samadi, K. (2009). Orion 2.0: A fast and accurate noc power and area model for early-stage design space exploration. In Proc. DATE 7809, pages 423-428.
  9. Kephart, J. and Chess, D. (2003). The vision of autonomic computing. Computer, 36(1):41-50.
  10. Keutzer, K., Newton, A., Rabaey, J., and SangiovanniVincentelli, A. (2000). System-level design: orthogonalization of concerns and platform-based design. IEEE Transactions on CAD, 19(12):1523-1543.
  11. Latif, K., Niazi, M., Tenhunen, H., Seceleanu, T., and Sezer, S. (2008). Application development flow for on-chip distributed architectures. In Proceeding of SOC Conference, 2008 IEEE International.
  12. Lee, E. A. (2008). Cyber physical systems: Design challenges. Technical Report UCB/EECS-2008-8, EECS Department, University of California, Berkeley.
  13. Lehtonen, T., Liljeberg, P., and Plosila, J. (2007). Online reconfigurable self-timed links for fault tolerant noc. VLSI Design, 2007:13.
  14. Lu, Z., Jantsch, A., Salminen, E., and Grecu, C. (2008). Network-on-chip benchmarking specification part 2: Microbenchmark specification version 1.0. Technical report, OCP International Partnership Association.
  15. Ogras, U., Marculescu, R., Marculescu, D., and Jung, E. G. (2009). Design and management of voltage-frequency island partitioned networks-on-chip. IEEE Transactions on VLSI, 17(3):330-341.
  16. Rabaey, J. M. (2004). Interconnect-centric Design for Advanced SoC and NoC, chapter System-on-chip challenges in the deep-sub-micron era, a case for the network-on-a-chip, pages 3-24. Kluwer Academic Publishers.
  17. Sangiovanni-Vincentelli, A. and Martin, G. (2001). Platform-based design and software design methodology for embedded systems. IEEE Des. Test, 18(6):23- 33.
  18. Shang, L., Peh, L., Kumar, A., and Jha, N. (2004). Thermal modeling, characterization and management of on-chip networks. In Proc. 37th International Symposium on Microarchitecture MICRO-37 2004, pages 67-78.
  19. Shang, L., Peh, L.-S., and Jha, N. (2003). Dynamic voltage scaling with links for power optimization of interconnection networks. In Proc. of HPCA 2003, pages 91-102.
  20. Stefanov, D. H., Bien, Z., and Bang, W.-C. (2004). The smart house for older persons and persons with physical disabilities: structure, technology arrangements, and perspectives. IEEE Transactions on Neural Systems and Rehabilitation Engineering, 12:228-250.
  21. Tierno, J., Rylyakov, A., and Friedman, D. (2008). A wide power supply range, wide tuning range, all static cmos all digital pll in 65 nm soi. IEEE Journal of Solid-State Circuits, 43(1):42-51.
  22. Truong, D., Cheng, W., Mohsenin, T., Yu, Z., Jacobson, A., Landge, G., Meeuwsen, M., Watnik, C., Tran, A., Xiao, Z., Work, E., Webb, J., Mejia, P., and Baas, B. (2009). A 167-processor computational platform in 65 nm cmos. IEEE Journal of Solid State Circuits, 44(4):1130-1144.
  23. Truscan, D., Seceleanu, T., Lilius, J., and Tenhunen, H. (2008). A model-based design process for the segbus distributed architecture. In Proceedings of the 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems, pages 307-316. IEEE Computer Society.
  24. Vangal, S., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Iyer, P., Singh, A., Jacob, T., Jain, S., Venkataraman, S., Hoskote, Y., and Borkar, N. (2007). An 80-tile 1.28tflops network-on-chip in 65nm cmos. In Proc. Digest of Technical Papers. of ISSCC 2007, pages 98-589.
  25. Wibben, J. and Harjani, R. (2007). A high efficiency dc-dc converter using 2nh on-chip inductors. In Proc. IEEE Symposium on VLSI Circuits, pages 22-23.
  26. W ürtz, R. P., editor (2008). Organic Computing. Springer.
  27. Yang, B., Guang, L., Canhao, X. T., Yin, A. W., Tero Säntti, T., and Plosila, J. (2010). Multi-application multi-step mapping method for many-core network-on-chips. In Proc. of Norchip 2010.
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Paper Citation


in Harvard Style

Guang L., Yang B., Plosila J., Isoaho J. and Tenhunen H. (2011). HIERARCHICAL AGENT MONITORING DESIGN PLATFORM - Towards Self-aware and Adaptive Embedded Systems . In Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: SAAES, (PECCS 2011) ISBN 978-989-8425-48-5, pages 573-581. DOI: 10.5220/0003396805730581


in Bibtex Style

@conference{saaes11,
author={Liang Guang and Bo Yang and Juha Plosila and Jouni Isoaho and Hannu Tenhunen},
title={HIERARCHICAL AGENT MONITORING DESIGN PLATFORM - Towards Self-aware and Adaptive Embedded Systems},
booktitle={Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: SAAES, (PECCS 2011)},
year={2011},
pages={573-581},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003396805730581},
isbn={978-989-8425-48-5},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: SAAES, (PECCS 2011)
TI - HIERARCHICAL AGENT MONITORING DESIGN PLATFORM - Towards Self-aware and Adaptive Embedded Systems
SN - 978-989-8425-48-5
AU - Guang L.
AU - Yang B.
AU - Plosila J.
AU - Isoaho J.
AU - Tenhunen H.
PY - 2011
SP - 573
EP - 581
DO - 10.5220/0003396805730581