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Affiliation

Chair of Computer Science 3 (Computer Architecture), Friedrich-Alexander Universitaet Erlangen-Nuernberg, Martensstr. 3, Erlangen, Germany

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1 Papers

Work in Progress: Extending Virtual Prototypes of Microprocessor Architectures with Accuracy Tracing

Topics: Real-Time Systems; Hardware/Software/Human in the Loop Simulation

Authors: Johannes Kliemt and Dietmar Fey

Affiliation: Chair of Computer Science 3 (Computer Architecture), Friedrich-Alexander Universitaet Erlangen-Nuernberg, Martensstr. 3, Erlangen, Germany

Digital Object Identifier: 10.5220/0012131800003546

Proceedings of SIMULTECH 2023, ISBN: 978-989-758-668-2

Quick Abstract

Virtual Prototypes of microprocessor architectures (VPs) extensively support the software development process with the ability to build virtual Hardware in the Loop (vHIL) test benches. A physical hardware is not necessary since the VP is also a functional simulation model, although with reduced accuracy. The actual deviation to the physical hardware in the time domain is mostly unspecified and dependent on the executed application software. This leads to issues when used in the development of software with real time requirements. The authors propose a new way of determining this inaccuracy via a trace unit integrated into the VP. Accuracy is now determined for each application software on the fly taking its individual paths through the model and not by a unrelated general set of accuracy benchmarks. A more reliable statement on the later temporal behavior on the physical hardware can therefore be given.