A Self-duty-cycled Digital Baseband for Energy-enhanced Wake-up
Receivers
Sadok Bdiri
1
, Oussama Brini
2
and Faouzi Derbel
1
1
Leipzig University of Applied Sciences, W
¨
achter Str. 13, 04107, Leipzig, Germany
2
National School of Electronics and Telecommunications of Sfax, Sfax, Tunisia
Keywords:
DBB, Digital Baseband, Wake-up Receiver, Wireless Sensor Network, WSN, Low-power, Duty-cycle.
Abstract:
An ultra low-power digital baseband (DBB) for Wake-up Receiver (WuRx) is presented. Based on low power
microcontroller (MCU), the DBB power gates the WuRx peripherals to further reduce their average energy
consumption. It issues low duty-cycling signals with very short power-on periods, allowing very low latency
between a transmitted WuPt and its detection. The latency and power consumption tradeoff can be adjusted to
meet different application requirements. The presented circuit implements low-power listening protocol as a
duty-cycle scheme and also emphasizes the possibility to decode more than 512-bit address pattern.
1 INTRODUCTION
A battery is an exhausting energy resource used by
wide range of devices. WSN feeds off batteries, thus
conserving energy is essential. Replacing or changing
batteries in WSN can be costly and difficult to realize.
In practical cases, the lifetime of a WSN reaches its
end when all devices (wireless sensor nodes) within
the network go permanently inaccessible. A depleted
battery can be one of the causes. Radio chip, in a
wireless node, consumes the most energy with ref-
erence to the rest of node’s components (i.e., sen-
sors, microcontroller (MCU)). The radio’s permanent
activity is often not necessary in WSN. Therefore,
switching it to sleep state can drastically preserve en-
ergy. To prevent a sensor node from being totally
disconnected from the network during the conven-
tional radio’s sleep period, a much lower power ra-
dio receiver can be used instead. The latter is re-
ferred to as (WuRx). Generally, its main purpose is to
continuously listen for an incoming wake-up packet
(WuPt). It is communicated from a different node.
Upon WuPt reception, the WuRx, then, issues an in-
terrupt to the MCU, which, in return, wakes-up the
main transceiver. WuRx should be based on simple
architectures to keep the overall complexity of a sen-
sor node to a minimum. Other characteristics are sen-
sitivity, data rate and energy usage. In a WSN where
each sensor node is embedded with a WuRx, the lat-
ter should distinguish between different WuPt. This
is done by including a unique destination address in
every WuPt. The DBB deals with the address pattern
correlation and issues a logic signal if it is addressed.
This way, unnecessary MCU active/sleep toggling is
avoided and more energy is saved.
Front-End
Interrupt
Analog Digital
Converter
Digital Baseband
Figure 1: Simplified typical WuRx block diagram.
Depending on how dense is the WSN, the WuPt
includes a unique pattern for every node, coded in 16,
32, 64 bits, etc. On-off keying (OOK) is often used
for modulation schemes as it allows low-complex ar-
chitectures. However, this can impact the overall
sensitivity and power demand of a WuRx. Several
DBBs are introduced in recent works to optimize the
mentioned features. (Bdiri and Derbel, 2015)(Gamm
et al., 2014) use AS3932 (Austrian Mikro Systeme,
2015a) or AS3933 (Austrian Mikro Systeme, 2015b)
as an off-the-shelf DBB. The chip eliminates the need
of a digitizer (i.e, comparator), meaning that it is able
to condition an analog representation of the pattern bit
sequence. The minimum sensitivity reaches down to
80 µV
RMS
. The chip consumes more than 5 µW when
listening and 24 µW during pattern decoding. The au-
thors in (Magno et al., 2016) used an MCU to deal
with the decoding mechanism. With no RF activity,
the MCU is at its lowest sleep state consuming 40 nW.
It activates the core at 8 MHz upon reception of the
WuPt preamble, followed by WuPt correlation, dur-
Bdiri, S., Brini, O. and Derbel, F.
A Self-duty-cycled Digital Baseband for Energy-enhanced Wake-up Receivers.
DOI: 10.5220/0006512600150018
In Proceedings of the 7th International Conference on Sensor Networks (SENSORNETS 2018), pages 15-18
ISBN: 978-989-758-284-4
Copyright © 2018 by SCITEPRESS Science and Technology Publications, Lda. All rights reserved
15
ing which, it drains 300 µW. This indicates that the
more WuPt the WuRx receives the more it consumes.
In (Mazloum et al., 2016), another design based
on flip-flops is introduced. The DBB is optimized
for a specific duty-cycled WuRx, specifically DCW-
MAC (Mazloum and Edfors, 2011). At 250 kbit s
1
,
it consumes 0.9 µW. A complex programmable logic
device (CPLD) and a field-programmable gate array
(FPGA) can be used to act as DBB for WuRx. The en-
ergy consumption, however, is still higher than most
of the introduced DBB (Pet
¨
aj
¨
aj
¨
arvi et al., 2016)(Jean-
Franc¸ois et al., 2013). In this work, a DBB for duty-
cycled WuRx is introduced. The detection procedure
is based on low-power listening (LPL) protocol (Po-
lastre et al., 2004). It is safe to say that the DBB is
fully flexible to implement different MAC protocols
depending on the application prerequisites. The intro-
duced DBB offers scalability in terms of address pat-
tern length, data rate and energy consumption. This
paper is organized as follows: In section II, details
and analysis of the design process are discussed. Sec-
tion III reports the measurements done on a fabricated
WuRx with the presented DBB. Finally, section IV
concludes the proposed work.
2 SYSTEM DESCRIPTION
The proposed solution relies on maximizing WuRx’s
sleep time instead of constantly monitoring the chan-
nel. It allows the adjustment of several parameters
such as destination address length, data rate and WuPt
detection latency. This flexibility makes the WuRx
suitable for a wide range of applications. A low-
power MCU PIC12LF1572 (Microchip, 2015) is used
to design the back-end of WuRx. The MCU period-
ically wakes-up then enables the rest of WuRx com-
ponents. If any RF signal is fed through the front-end
during this brief time duration T
ON
, the MCU waits
for a corresponding WuPt preamble. If it is the case,
it keeps the active components active to receive the
rest of WuPt. A decision is made depending on the
correlation results followed by switching off all ac-
tive components. The MCU switches to sleep state
for T
S
until the next wake-up period. The MCU waits
for preamble detection during T
ON
. The power dy-
namically increases proportionally with the number
of successful preamble detections.
In the case where there is no WuPt, all compo-
nents are turned off and the MCU turns back to sleep.
Fig. 2 illustrates the timing diagram where the MCU
successfully detects/misses a WuPt. The illustrated
arrival time of the WuPt is considered the best case
scenario as the MCU activates for the minimum nec-
t
...
t
T
S
...
T
ON
MCU
WuTx
Preamble SB
ID
Sleep(WDT)
Active
T
d
Figure 2: Simplified timing diagram of WuPt and duty-
cycled MCU in channel listening.
essary time T
d
. The opposite case is when the pream-
ble is detected at the very beginning of the WuPt.
Then, the MCU has to process the entire WuPt, wast-
ing more energy. Let β be the mean interval between
two transmitted WuPts. The DBB’s average power
consumption is calculated as follows:
P
avg
=
P
ON
(βT
ON
+ T
S
(T
d
T
ON
)) +P
WDT
T
S
(β + T
ON
T
d
)
β(T
ON
+ T
S
)
(1)
where P
ON
and P
WDT
are the power consumption of the
MCU at active state and sleep with watchdog enabled,
respectively. The detection is performed in a purely
asynchronous scheme. OOk is employed for a low-
power front-end architecture.
2.1 WuPt Structure
The WuPt contains a preamble, separation bits (SB)
and destination address pattern (ID). The preamble
{p
0
. . . p
i1
, i N}, consisting of i-bit, helps the
MCU detect the presence of WuPt. SB {s
0
. . . s
j1
,
j N} are composed of j-bit. The sequence sepa-
rates preamble and the ID.
Start bit d
0
d
1
d
7
Stop Bit
Figure 3: 8-bit ID sequence diagram.
Let k N. The ID consists of k times 10-bit se-
quence where {d
0
. . . d
7
} are the 8-bit ID and 2 bits
for a start and stop bits. k = 2 and k = 4 represent
16-bit and 32-bit IDs, respectively. Depending on the
memory of the MCU, the latter can decode more than
512-bit. The start and the stop bits help the MCU lo-
calize the pattern.
2.2 Back-end Architecture
Instead of continuously waiting for an incoming
WuPt, the self-duty cycled MCU wakes-up periodi-
cally to monitor the channel. When the MCU enters
sleep state, all its internal peripherals are automati-
cally disabled except for the watchdog timer (WDT).
By enabling the latter, the MCU can toggle between
SENSORNETS 2018 - 7th International Conference on Sensor Networks
16
active/sleep state without the need for an external
timer. The more interesting characteristic of the WDT
lies in its energy consumption with only 260 nA at
1.8 V. When WDT overflows, the MCU is interrupted
and switches to active state. The WDT’s time-out rep-
resents also the sleep period t
S
of the WuRx. This can
be configured between 1 ms and 256 s (Microchip,
2015). When the MCU enables all active elements of
the WuRx, it holds waiting for a WuPt preamble (i.e.,
’010101...’) till an elapsed duration of T
ON
. Upon the
reception of the preamble, the MCU counts the pos-
itive edges of each single p
i1
bit for i
c
times. The
counting stops if it reaches n (i
c
= n), where n is a
user-defined number of positive edges the MCU has
to detect. If i
c
< n, the detection is considered erro-
neous, then the MCU turns-off all external peripherals
and switches back to sleep.
Any interfering signal, that has a baseband fre-
quency higher or lower than f
c
, is rejected by the
MCU by means of digital filtering. This is done by
continuously polls an input pin for a certain period
of time t
p
, in a way that if the positive edge comes
sooner or later than expected the preamble is rejected.
Let f
c
be the modulated signal frequency. The choice
t
p
is done by the following equation.
1
f
c
< t
p
<
2
f
c
(2)
The choice of T
ON
depends on t
p
and the power-on
time t
POWER
of all peripherals including the MCU. The
minimum T
ON
should obey the Eq. 3.
t
POWER
+t
p
< T
ON
(3)
In the different case of successful preamble detection,
the MCU remains active and waits for s
j1
-bit. The
SB structure is a successive j of ’1’ bits. If SB se-
quence is received, the MCU enables the enhanced
universal synchronous asynchronous receiver trans-
mitter (EUSART). The latter is a peripheral within the
MCU dedicated for serial communication. The usage
of EUSART excludes the need of a software imple-
mentation for serial data reception. The correlation
process starts upon reception of the first ’0’ bit (start
bit) after SB. The EUSART stores the {d
0
. . . d
7
} in
a byte register to be read later on. The process is re-
peated k times until the processing of all ID frame
takes place. The MCU, then, compares the received
byte(s) to the stored value(s). The comparison brings
the decision to either issue an interrupt or not to an
external unit. In the end, the MCU disables the EU-
SART and all WuRx’s peripherals. The decoding pro-
cess takes time T
d
and affects dynamically the average
power consumption of DBB. In the following section,
we configure the MCU with the required parameters
to evaluate its performance.
3 SYSTEM EVALUATION
Figure 4: Assembled wake-up receiver with the presented
DBB on 1.55 mm thick printed circuit board (PCB).
The front-end published in (Bdiri et al., 2016) is
used to implement and evaluate the DBB. It consists
of an envelope detector that performs an RF to DC
conversion. Then an amplifier boosts the signal an
forward it to an analog to digital convertor. In the end,
the logic signal is fed to the DBB. Only the electrical
characteristics of the MCU are taken into account for
the final measurements. Fig. 4 shows all the assem-
bled components on a PCB. T
S
represents the latency
of WuPt detection since at that time the DBB is at
sleep state. It is configured by acting on the watchdog
timer. For the sake of the complete system evaluation,
the DBB it is set to perform preamble detection ev-
ery T
S
= 32 ms. Moreover, when exiting sleep mode,
the high frequency internal oscillator (HFINTOSC)
is activated, which requires a certain time to stabi-
lize. For the PIC12LF1572, the HFINTOSC warm-up
time t
POWER
= 5 µs. 16 MHz is chosen for the core fre-
quency to allow maximum processing speed at which,
the MCU demands a power P
ON
= 1mW. 32 MHz
requires a phase locked loop (PLL) and needs more
than 2 ms to settle. The WuPt modulated frequency
is chosen f
c
= 128 kHz. From Eq. 2, t
p
is calculated
t
p
= 8 µs. Hence, from Eq. 3, T
ON
= 13 µs. Using these
parameters on the Eq. 1, P
av
can be simulated against
the mean average interval β for minimum and maxi-
mum durations of T
d
. The latter depends on the WuPt
arrival time and when it coincides with the MCU’s
preamble polling. Fig. 5 shows the obtained results.
For β > 1000 s the average power is P
av
< 0.9µW for
T
S
= 32 ms.
The MCU is configured to correlate a 24-bit ID
{0x55, 0x69, 0x96}. Fig. 6 shows a successful de-
coding process finished by issuing a pulse at an output
pin.
The duty-cycle obeys the LPL protocol. This can
cause overhearing issues in a dense WSN, thus in-
creasing energy consumption. The DBB allows flexi-
ble implementation of different MAC protocols as to
A Self-duty-cycled Digital Baseband for Energy-enhanced Wake-up Receivers
17
1E-1 1 1E1 1E21E-2 1E3
10
100
1000
1
4000
ß(second)
Pa(µW)
P
av
(T
d
=280µs)
P
av
(T
d
=32ms)
Figure 5: The MCU’s average power consumption against
the mean interval time β for different decoding durations
T
d
.
Figure 6: Oscilloscope screen capture of a correlated
WuPt’s ID (blue). A generated pulse (pink) indicates a
matching ID with the register values
address specific applications demands.
4 CONCLUSION
An MCU-based back-end for duty-cycled wake-up re-
ceivers is introduced. It operates as a DBB with ad-
dressing capabilities and also controls the activity of
WuRx peripherals to reduce the overall energy con-
sumption. The MCU is fully configurable either by
an external unit or by acting on its firmware. Main
configuration parameters including latency, data rate
and ID length allow a wide range of input values. A
prototype is realized as to evaluate the the intended
features. For a latency of T
S
= 32 ms, the DBB con-
sumes less than 1 µW. The power consumption de-
pends on timing parameters, which can be configured
depending on the application requirements. Addition-
ally, several MAC protocols can be implemented to
improve different performance measures, including
energy consumption, overhearing issues and latency.
REFERENCES
Bdiri, S. and Derbel, F. (2015). An Ultra-Low Power Wake-
Up Receiver for Realtime constrained Wireless Sensor
Networks. AMA Conferences 2015, Nurenberg, Ger-
many, pages 612–617.
Bdiri, S., Derbel, F., and Kanoun, O. (2016). An 868 MHz
7.5 µW Wake-up Receiver with 60 dBm Sensitivity.
Journal of Sensors and Sensor Systems, 5(2):433–446.
Gamm, G. U., Stoecklin, S., and Reindl, L. M. (2014).
Wake-up receiver operating at 433 MHz. In 2014
IEEE 11th International Multi-Conference on Sys-
tems, Signals & Devices (SSD14). Institute of Elec-
trical & Electronics Engineers (IEEE).
Jean-Franc¸ois, P., Jean-Jules, B., and Yvon, S. (2013).
Modeling, design and implementation of a low-power
FPGA based asynchronous wake-up receiver for wire-
less applications. Analog Integrated Circuits and Sig-
nal Processing, 77(2):169–182.
Magno, M., Jelicic, V., Srbinovski, B., Bilas, V., Popovici,
E. M., and Benini, L. (2016). Design, implementation,
and performance evaluation of a flexible low-latency
nanowatt wake-up radio receiver. IEEE Trans. Indus-
trial Informatics, 12(2):633–644.
Mazloum, N. S. and Edfors, O. (2011). DCW-MAC: an
energy efficient medium access scheme using duty-
cycled low-power wake-up receivers. In Proceedings
of the 74th IEEE Vehicular Technology Conference,
VTC Fall 2011, 5-8 September 2011, San Francisco,
CA, USA, pages 1–5.
Mazloum, N. S., Rodrigues, J. N., Andersson, O., Nejdel,
A., and Edfors, O. (2016). Improving practical sensi-
tivity of energy optimized wake-up receivers: proof of
concept in 65nm CMOS. CoRR, abs/1605.00113.
Austrian Mikro Systeme (2009 [Revised 2015]a).
110 150 KHz AS3932 3D Low Fre-
quency Wakeup Receiver, datasheet.
http://ams.com/chi/content/download/23636/413647/.
Austrian Mikro Systeme (2010 [Revised 2015]b). 15
150 KHz AS3932 3D Low Frequency Wakeup
Receiver, datasheet. http://ams.com/eng/Wake-up-
receiver/AS3933.
Microchip (2013 [Revised 2015]). PIC12F1572 - 8-bit
PIC Microcontrollers, datasheet. http://ww1.micro
chip.com/downloads/en/DeviceDoc/40001723D.pdf.
Pet
¨
aj
¨
aj
¨
arvi, J., Mikhaylov, K., Vuohtoniemi, R., Karvonen,
H., and Iinatti, J. (2016). On the human body commu-
nications: wake-up receiver design and channel char-
acterization. EURASIP Journal on Wireless Commu-
nications and Networking, 2016(1):1–17.
Polastre, J., Hill, J. L., and Culler, D. E. (2004). Versatile
low power media access for wireless sensor networks.
In Proceedings of the 2nd International Conference on
Embedded Networked Sensor Systems, SenSys 2004,
Baltimore, MD, USA, November 3-5, 2004, pages 95–
107.
SENSORNETS 2018 - 7th International Conference on Sensor Networks
18