Mature 25Gb/s Silicon Photonic Platform towards Multi-Layer Circuits for High Integration Level Aplications

C. Kopp, B. Szelag, D. Fowler, C. Dupre, K. Hassan, C. Baudot

Abstract

Silicon photonics is definitely a key technology in next-generation communication systems from Long-Haul networks to short reach data interconnects. To address 25 Gb/s and above applications, we present our R&D platform that uses a CMOS foundry line. The fabrication process is following a modular integration scheme which leads to a flexible platform, allowing various device combinations. Moreover this platform is associated to a device library in a PDK which includes specific photonic features and which is compatible with commercial EDA tools. Based on the maturity of this platform to build high-speed optical transceivers, we present our strategy to anticipate the next integration disruptive level by implementing multi-layer photonic circuits. Such a technology represents a new paradigm for the design of very high integration circuits that we consider first for optical interposer, and finally for optical network on chip with the convergence of photonics and electronics.

References

  1. Kopp, C., 2011. Silicon Photonic Circuits: On-CMOS Integration, Fiber Optical Coupling, and Packaging. IEEE Journal of Selected Topics in Quantum Electronics, vol. 17, no. 3, pp. 498-509, May 2011.
  2. Baudot, C., 2016. DAPHNE silicon photonics technological platform for research and development on WDM applications. 2016, vol. 9891, p. 98911D98911D-18.
  3. Boeuf, F., 2015. Recent Progress in Silicon Photonics R&D and Manufacturing on 300mm Wafer Platform. Optical Fiber Communication Conference, OSA Technical Digest (online) (Optical Society of America, 2015), paper W3A.1.
  4. Martin, P., 2014. Modeling of Silicon Photonics Devices with Verilog-A. Proc. MIEL 2014, pp 209-212.
  5. Cibrario, G., A High-Level Design Rule Library Addressing CMOS and Heterogeneous Technologies. IEEE ICICDT 2014.
  6. Cao, R., 2014. Silicon Photonics Design Rule Checking: Application of a Programmable Modeling Engine for Non-Manhattan Geometry Verification. VLSI-SoC 2014.
  7. Duprez, H., 2016. Hybrid IIIV on Silicon Laterally Coupled Distributed Feedback Laser Operating in the -Band. IEEE Photonics Technology Letters, vol. 28, no. 18, pp. 1920-1923, Sep. 2016.
  8. Thonnart, Y., 2014. Technology assessment of silicon interposers for manycore SoCs: Active, passive, or optical?. Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2014, pp. 168-169.
  9. Testa, F., 2016. Design and Implementation of an Integrated Reconfigurable Silicon Photonics Switch Matrix in IRIS Project. IEEE Journal of Selected Topics in Quantum Electronics, vol. 22, no. 6, pp. 1-14, Nov. 2016.
  10. Bernabé, S., 2016. Packaging of Photonic Integrated Circuit Based High-Speed Coherent Transmitter Module. 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, pp. 1081-1086.
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Paper Citation


in Harvard Style

Kopp C., Szelag B., Fowler D., Dupre C., Hassan K. and Baudot C. (2017). Mature 25Gb/s Silicon Photonic Platform towards Multi-Layer Circuits for High Integration Level Aplications . In Proceedings of the 5th International Conference on Photonics, Optics and Laser Technology - Volume 1: PHOTOPTICS, ISBN 978-989-758-223-3, pages 76-81. DOI: 10.5220/0006147700760081


in Bibtex Style

@conference{photoptics17,
author={C. Kopp and B. Szelag and D. Fowler and C. Dupre and K. Hassan and C. Baudot},
title={Mature 25Gb/s Silicon Photonic Platform towards Multi-Layer Circuits for High Integration Level Aplications},
booktitle={Proceedings of the 5th International Conference on Photonics, Optics and Laser Technology - Volume 1: PHOTOPTICS,},
year={2017},
pages={76-81},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0006147700760081},
isbn={978-989-758-223-3},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 5th International Conference on Photonics, Optics and Laser Technology - Volume 1: PHOTOPTICS,
TI - Mature 25Gb/s Silicon Photonic Platform towards Multi-Layer Circuits for High Integration Level Aplications
SN - 978-989-758-223-3
AU - Kopp C.
AU - Szelag B.
AU - Fowler D.
AU - Dupre C.
AU - Hassan K.
AU - Baudot C.
PY - 2017
SP - 76
EP - 81
DO - 10.5220/0006147700760081