Authors:
Tian Song
and
Takashi Shimamoto
Affiliation:
Tokushima University, Japan
Keyword(s):
Motion Compensation, RDO, H.264, VLSI.
Related
Ontology
Subjects/Areas/Topics:
Image and Video Processing, Compression and Segmentation
;
Multimedia
;
Multimedia Signal Processing
;
Telecommunications
Abstract:
In this paper, a novel motion compensation architecture is proposed to support the Rate-Distortion Optimization(RDO) in H.264/AVC. First, the scope of the motion compensation in this work is defined not only including the half and quarter pixel motion compensation but also the deblocking filter and rate-distortion optimazation. Then, base on the new concept of motion compensation an efficient architecture for H.264/AVC codec is constructed. Proposed architecture could select the best mode for INTRA macroblocks using the lagrange function by calculating the distortion and the generated bits. It could also calculate the lagrange function for INTER macroblocks by receiving the motion vector information and the interpolation data from the ME(Motion Estimation) module to construct a complete rate distortion optimization architecture. Pipelined processing structure is designed for sub-block mode selection to achieve real-time processing for up to HDTV resolution inputs. Implementation resu
lt shows that proposed architecture could be realized with only 42,280 gates and 48,320 bits SRAM.
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