Patterns System for the Design of Partial Reconfigurable Applications on FPGA

Nissaf Fredj, Mhamed Saidane, Yessine Hadj Kacem, Mohamed Abid

Abstract

During the last few years, the Dynamic Partial Reconfiguration (DPR) has been introduced to the embedded systems as a key technique that aims at improving the flexibility of Field-Programmable Gate Array (FPGA)-based system reconfiguration. However, the design of these systems is a hard task using low-level functions where the design of the hardware side precedes that of the software. Recently, Model-Driven Engineering (MDE) based approaches have emerged. They aim at simplifying the modeling of the dynamically set systems and keep a design flow where DPR application and architecture are designed in parallel. In fact, there is a lack of reusable and generic models that allow the improvement of the designers’ task and the decrease of the development costs. In order to overcome these issues we propose in this paper an additional featuring or abstraction level in the DPR design flow introduced by these approaches. Our aim is to suggest for designers a method (process and models) which allows reusing recurrent application models and sharing experience-owned knowledge. The proposed method is a patterns system which is a combination of architectural and behavioral patterns dedicated to the Dynamic Partial reconfigurable Real-Time Embedded (DP-RTE) systems.

References

  1. Beux, S. L. (2007). Un flot de conception pour les applications de traitement du signal systematique implementees sur fpga a base d ingenierie dirigee par les modeles. Universite des Sciences et Technologie de Lille.
  2. Buschmann, F., Meunier, R., Rohnert, H., Sommerlad, P., and Stal, M. (1996). Pattern- oriented software architecture. Wiley.
  3. Cherif, S. (2013). Approche basee sur les modeles pour la conception des systèmes dynamiquement reconfigurables: de MARTE vers RecoMARTE. University of Science and Technology of Lille.
  4. Cherif, S. Chiraz, T., Samy, M., and Dekeyser, J. (nov 2011). High level design of adaptive distributed controller for partial dynamic reconfiguration in fpga. Conference on Design Architectures for Signal Image Processing: DASIP, pages 308-315.
  5. Chiraz, T. (2012). Controle materiel des systemes partiellement reconfigurables sur fpga: de la modelisation a l implementation.
  6. Corsaro, A., Schmidt, D. C., Klefstad, R., and ORyan, C. (2002). Design pattern for memory-constrained embedded applications. Proceedings of the 9th Conference on Pattern Language of Programs.
  7. Gamatie, A., Beux, S. L., Piel, E., Etien, A., Atitallah, R. B., Marquet, P., and Dekeyse, J.-L. (aout 2008). A model driven design framework for high performance embedded systems. INRIA Journal.
  8. Gamma, E., Helm, R., and Johnson, R. (1995). Design patterns: Elements of reusable object-oriented software. Addison Wesley. .
  9. Group, O. M. (2003). UML 2.0 OCL Specification. OMG Adopted Specification ptc/03-10-14. Object Management Group.
  10. Group, O. O. M. (June 2011). A UML Profile for MARTE: Modeling and Analysis of Real-Time Embedded systems, ptc/2011-06-02. Object Management Group.
  11. Henzinger, T. A. and Sifakis, J. (2007). The discipline of embedded systems design. IEEE Society Computer.
  12. Imran Rafiq Quadri, Abdoulaye Gamatie, S. M. J.-L. D. H. Y. E. R. (jan 2010). Targeting reconfigurable fpga based socs using the uml marte profile: from high abstraction levels to code generation. INRIA Journal, pages 308-315.
  13. Marques, N. (2012). Methodologie et architecture adaptative pour le placement efficace de taches materielles de tailles variables sur des partitions reconfigurables.
  14. M. Chess, J. O. K. D. (2003). The vision of autonomic computing. IEEE Computer Society. Ochoa-Ruiz, G., Labbani, O., Bourennane, E.-B., Soulard.
  15. Ochoa-Ruiz G, Ouassila L, El-Bay B, Philippe S and Sana C. (2012) A High-level Methodology for Automatically Generating. Springer Verlag (Germany).
  16. Rolland, C. Foucault, O. and Guillaume, B. (1988). Conception des Systèmes d'Information - la méthode REMORA. Editions Eyrolles.
  17. Said, M. B., Kacem, Y. H., Kerboeuf, M., Amor, N. B., and Abid, M. (July 2014). Design patterns for selfadaptive systems specification. International Journal of Reconfigurable Computing.
  18. Schmidt, D., Stal, M., Rohnert, H., and Buschmann, F. (2000). Pattern-oriented software architecture, patterns for concurrent and networked objects, volume 2. Wiley.
  19. . Vogel, T., Seibel, A., and Giese, H. (2011). The role of models and megamodels at runtime. Springer.
  20. Thomas V., Andreas S and Holger G. (2011). The Role of Models and Megamodels at Runtime. Springer.
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Paper Citation


in Harvard Style

Fredj N., Saidane M., Kacem Y. and Abid M. (2017). Patterns System for the Design of Partial Reconfigurable Applications on FPGA . In Proceedings of the 12th International Conference on Evaluation of Novel Approaches to Software Engineering - Volume 1: MDI4SE, ISBN 978-989-758-250-9, pages 325-335. DOI: 10.5220/0006383503250335


in Bibtex Style

@conference{mdi4se17,
author={Nissaf Fredj and Mhamed Saidane and Yessine Hadj Kacem and Mohamed Abid},
title={Patterns System for the Design of Partial Reconfigurable Applications on FPGA},
booktitle={Proceedings of the 12th International Conference on Evaluation of Novel Approaches to Software Engineering - Volume 1: MDI4SE,},
year={2017},
pages={325-335},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0006383503250335},
isbn={978-989-758-250-9},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 12th International Conference on Evaluation of Novel Approaches to Software Engineering - Volume 1: MDI4SE,
TI - Patterns System for the Design of Partial Reconfigurable Applications on FPGA
SN - 978-989-758-250-9
AU - Fredj N.
AU - Saidane M.
AU - Kacem Y.
AU - Abid M.
PY - 2017
SP - 325
EP - 335
DO - 10.5220/0006383503250335