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Authors: Soumyadip Bandyopadhyay 1 ; Santonu Sarkar 1 and Kunal Banerjee 2

Affiliations: 1 BITS Pilani and K K Birla Goa Campus, India ; 2 Indian Institute of Technology, India

ISBN: 978-989-758-262-2

Keyword(s): Equivalence Checking, Petri Net based Representation for Embedded Systems (PRES+) Model, Finite State Machine with Datapath (FSMD) Model, High-level Language.

Related Ontology Subjects/Areas/Topics: Distributed and Mobile Software Systems ; Formal Methods ; Model Tools ; Models ; Paradigm Trends ; Parallel and High Performance Computing ; Programming Languages ; Simulation and Modeling ; Software Engineering ; Software Engineering Methods and Techniques

Abstract: Among the various models of computation (MoCs) which have been used to model parallel programs, Petri net has been one of the mostly adopted MoC. The traditional Petri net model is extended into the PRES+ model which is specially equipped to precisely represent parallel programs running on heterogeneous and embedded systems. With the inclusion of multicore and multiprocessor systems in the domain of embedded systems, it has become important to validate the optimizing and parallelizing transformations which system specifications go through before deployment. Although PRES+ model based equivalence checkers for validating such transformations already exist, construction of the PRES+ models from the original and the translated programs was carried out manually in these equivalence checkers, thereby leaving scope for inaccurate representation of the programs due to human intervention. Furthermore, PRES+ model tends to grow more rapidly with the program size when compared to other MoCs, suc h as FSMD. To alleviate these drawbacks, we propose a method for automated construction of PRES+ models from high-level language programs and use an existing translation scheme to convert PRES+ models to FSMD models to validate the transformations using a state-of-the-art FSMD equivalence checker. Thus, we have composed an end-to-end fully automated equivalence checker for validating optimizing and parallelizing transformations as demonstrated by our experimental results. (More)

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Paper citation in several formats:
Bandyopadhyay S., Sarkar S. and Banerjee K. (2017). An End-to-end Formal Verifier for Parallel Programs.In Proceedings of the 12th International Conference on Software Technologies - Volume 1: ICSOFT, ISBN 978-989-758-262-2, pages 388-393. DOI: 10.5220/0006464503880393

@conference{icsoft17,
author={Soumyadip Bandyopadhyay and Santonu Sarkar and Kunal Banerjee},
title={An End-to-end Formal Verifier for Parallel Programs},
booktitle={Proceedings of the 12th International Conference on Software Technologies - Volume 1: ICSOFT,},
year={2017},
pages={388-393},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0006464503880393},
isbn={978-989-758-262-2},
}

TY - CONF

JO - Proceedings of the 12th International Conference on Software Technologies - Volume 1: ICSOFT,
TI - An End-to-end Formal Verifier for Parallel Programs
SN - 978-989-758-262-2
AU - Bandyopadhyay S.
AU - Sarkar S.
AU - Banerjee K.
PY - 2017
SP - 388
EP - 393
DO - 10.5220/0006464503880393

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